FPGA Feasibility Study
Architecture/Concept Design
Technology Selection
Full FPGA Development
Block/IP Level FPGA Development
IP Integration
Design Modification/Optimization
FPGA Design Simulation/Test Benches
FPGA Design Verification
Hardware/Firmware Verification & Quality Assurance
Timing Closure
FPGA Debugging & Bringing Up In Lab
FPGA & Product Integration
FPGA Support & Field Upgrades
ASIC Porting
Xilinx, Inc.
Ultrascale, Ultrascale Plus, MPSOC
7 series Virtex 7 & Kintex – 7
Zynq
Virtex-E/2/4/5 & 6
Spartan-6
Sprtan-3/3E/3A/3AN/3ADSP
CPLD
Altera (Intel)
Stratix II, III, IV, Stratix V GT & Stratix V GS
Arria GX, Aria II, Aria V GX
Cyclone II, III, IV, V, Cyclone V SoC
MAX II & MAX V CPLD
Tools & Languages Utilized and Supported
Programming Languages
Python, C++, System C, Embedded C
VHDL, Verilog and System Verilog
FPGA Development Tools
Xilinx Vivado™ and ISE
Vivado™ HLS
MicroBlaze™
ChipScope
Altera (Quartus® II, Max+Plus® II)
Mentor Graphics® Questa ®
NC-Sim, ModelSim
Matlab/Simulink
Synplify Pro®
Synopsys Design Compiler
